Low-Power Design of Nanometer FPGAs: Architecture and EDA (Systems on Silicon)

Low-Power Design of Nanometer FPGAs: Architecture and EDA (Systems on Silicon)

Hassan Hassan


Low-Power layout of Nanometer FPGAs structure and EDA is a useful reference for researchers and working towards engineers desirous about power-efficient, FPGA layout. state of the art strength aid strategies for FPGAs may be defined and in comparison. those concepts may be utilized on the circuit, structure, and digital layout automation degrees to explain either the dynamic and leakage energy assets and allow concepts for codesign.

  • Low-power innovations awarded at key FPGA layout degrees for circuits, architectures, and digital layout automation, shape severe, "bridge" instructions for codesign
  • Comprehensive evaluate of leakage-tolerant strategies empowers designers to lessen strength dissipation
  • Provides necessary instruments for estimating energy efficiency/savings of present, low-power FPGA layout techniques

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